A key technical contributor on ASIC and IP development projects, working very closely with the ASIC engineering management to define and implement digital IP designs and integrate these and 3rd party designs into customer ASICs and SoCs.
The role involves working with customer requirements and providing technical advice and solutions in collaboration with multi-site development teams in producing high-quality designs.
The candidate will co-ordinate and contribute to the technical elements of the design process using a range of hardware description languages and tools. The candidate will also be involved in providing verification support based on their microarchitectural knowledge and ensuring clear communication of risks and issues to other teams using a variety of media, including high quality documentation.
Keep up to date with relevant engineering advances in the field and ensure that Sondrel is kept at the forefront of the state-of-the-art technologies, methodologies and design processes as used in the industry. Provide technical and practical support to junior team members to assist them in resolving problems and developing skills. Drive the analysis of customer requirements and implementation of functional digital designs and integration flows for complex SoCs. Collaborate with all engineering disciplines, providing traceable communication of issues, advice and suggestions. Support engineering management team in the co-ordination of designs and methodologies across the company and provide programme management team with realistic estimates of technical risks and design effort. Duties & Activities:
Development, maintenance and deployment of proprietary scripts and tools used in the design and database management of ASICs/SoCs. Deployment of industry-leading EDA tools for design quality assurance, power optimisation, constraints generation and synthesis/timing analysis Collaborate with architects to define microarchitecture of IPs and translation into sound, efficient RTL designs. Also provide innovative solutions to complex SoC integration issues. Communicate effectively with wider engineering teams and provide communication channels for less experienced engineers Create and present technical papers for internal or external distribution Qualifications:
A degree/masters or PhD in either a relevant or non-relevant subject Skills & Experience:
Minimum of 5 years’ experience; Follows broad instructions Excellent knowledge of digital design concepts Contributes to technical projects with limited guidance Provide technical guidance and communication channels to Consultant engineers Some ability to work independently but will work as part of a team. Solves problems of moderate-advanced complexity Applies judgment in interpreting results and conducting quantitative analysis Integrates thorough technical knowledge within discipline Interacts with more experienced team members and managers to resolve complex problems Applies knowledge of multiple sub function(s) May lead or train others on the team Contributes to technical white papers Contributes to sales support as part of a team effort Desirable:
HDL coding - VHDL, Verilog, System Verilog System design knowledge – clock domain management, reset schemes and power management Design for Test Design checking – Lint, CDC Power intent– UPF and or CPF Synthesis and constraints generation SoC level verification – HW/SW co-verification, multi-mode simulation, Gate-level simulation Database Management Perl, Python, Java, Tcl, IP-XACT Attributes:
Excellent communication and time management skills Self-organisation and ability to respond to changing priorities quickly Team player and self-motivated Ability to work under pressure Organisation and problem-solving skills Excellent attention to detail Able to work under own initiative A willingness to travel on an occasional basis and work the required hours « Return to the search results